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8-bit single-chip microcontrollers hms87c1304(2)a hms87c1204(2)a hms87c1104(2)a users manual apr. 2001 ver 1.0
hms87c130xa/120xa/110xa apr. 2001 ver1.0 1. overview ................................................................................................................... .... 1 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. block diagram ........................................................................................................... 4 3. pin assignment ........................................................................................................... 5 4. package diagram ...................................................................................................... 6 5. pin function ............................................................................................................... .. 9 6. port structures ..................................................................................................... 11 7. electrical characteristics .............................................................................. 16 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.3 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. memory organization ........................................................................................... 22 8.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 8.2 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.4 addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9. i/o ports .................................................................................................................. .... 34 9.1 ra and raio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 rb and rbio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3 rc and rcio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.4 rd and rdio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10. clock generator ................................................................................................. 38 10.1 oscillation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11. basic interval timer ............................................................................................ 40 12. timer / counter ...................................................................................................... 41 12.1 8-bit timer/counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 12.2 16-bit timer/counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.3 8-bit compare output (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.4 8-bit capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.5 16-bit capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.6 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13. buzzer output function .................................................................................... 50 14. analog to digital converter .......................................................................... 51 15. interrupts ............................................................................................................... 5 4 15.1 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.2 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 16. watchdog timer .................................................................................................... 59 17. power saving mode .............................................................................................. 60 17.1 minimizing current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 18. reset ..................................................................................................................... ..... 66 19. power fail processor ........................................................................................ 68 20. otp programming .................................................................................................. 70 20.1 device configuration area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 appendix instruction map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
hms87c130xa/120xa/110xa apr. 2001 ver1.0 1 HMS87C1304A / hms87c1302a hms87c1204a / hms87c1202a hms87c1104a / hms87c1102a cmos single-chip 8-bit microcontroller 1. overview 1.1 description the hms87c1x0xa is an advanced cmos 8-bit microcontroller with 4k/2k bytes of eprom. the hynix hms87c1x0xa is a powerful microcontroller which provide a highly flexible and cost effective solution to many small applications such as controller for battery charger. the hms87c1x0xa provides the following standard features: 4k/2k bytes of eprom, 128bytes of ram, 8-bit timer/counter, 8-bit a/d converter, 10-bit high speed pwm output, programmable buzzer driving port, power-on reset circuit, on-chip oscillator and clock circuitry. in addition, the hms87c1x0xa supports power saving modes to reduce power consumption. this document is only explained for the base of HMS87C1304A , the others eliminated functions are same as below. 1.2 features ? 4k/2k bytes on-chip program memory ? 128 bytes of on-chip data ram (included stack memory) ? instruction cycle time: - 250ns at 8mhz ? programmable i/o pins (led direct driving can be source and sink) - HMS87C1304A/1302a : 19 - hms87c1204a/1202a : 15 - hms87c1104a/1102a : 11 ? 2.0v to 5.5v wide operating range ? 8-bit a/d converter - 8 channels ? one 8-bit basic interval timer ? two 8-bit timer / counters ? one 10-bit high speed pwm outputs ? watchdog timer ? seven interrupt sources - external input: 2 ( 1 for hms87c1104/2a ) - a/d conversion: 1 - timer: 4 ? one programmable buzzer driving port ( except hms87c1104/2a ) - 500hz ~ 130khz device name eprom ram ext.int buz i/o operating voltage package HMS87C1304A 4k bytes 128bytes 2 o 19 2.0 ~ 5.5v 24 skdip or sop hms87c1302a 2k bytes 128bytes 2 o 19 2.0 ~ 5.5v 24 skdip or sop hms87c1204a 4k bytes 128bytes 2 o 15 2.0 ~ 5.5v 20 pdip or sop hms87c1202a 2k bytes 128bytes 2 o 15 2.0 ~ 5.5v 20 pdip or sop hms87c1104a 4k bytes 128bytes 1 x 11 2.0 ~ 5.5v 16 pdip or sop hms87c1102a 2k bytes 128bytes 1 x 11 2.0 ~ 5.5v 16 pdip or sop
2 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa ? oscillator type - crystal - ceramic resonator - rc-oscillation ( c can be omitted ) ? power-on reset ? noise immunity circuit - power fail processor ? power down mode - stop mode - wake-up timer mode - internal rc-wdt mode 1.3 development tools the hms87c1x0xa is supported by a full-featured mac- ro assembler, an in-circuit emulator choice-dr tm and otp programmers. the marco assembler operates under the ms-windows 95/ 98 tm . the otp programmer can be supplied three types of pro- grammer such as emulator add-on board type single pro- grammer (dr.writer tm ), univeral stand-alone type single programmer (choice-sigma tm ) and gang type pro- grammer (choice-sigma tm ). . figure 1-1 in circuit emulator choice-dr. tm figure 1-2 otp single programmer dr.writer tm figure 1-3 otp gang programmer choice-gang4 tm in circuit emulators choice-dr. tm assembler hynix macro assembler otp programmer single programmer : dr. writer tm universal programmer : choice- sigma tm gang programmer : choice-gang4 tm
hms87c130xa/120xa/110xa apr. 2001 ver1.0 3 1.4 ordering information rom size package type ordering device code operating temperature 4k bytes (otp) 24 skdip HMS87C1304A sk -20 ~ +85 c 24 sop HMS87C1304A d 20 pdip hms87c1204a 20 sop hms87c1204a d 16 pdip hms87c1104a 16 sop hms87c1104a d 2k bytes (otp) 24 skdip hms87c1302a sk 24 sop hms87c1302a d 20 pdip hms87c1202a 20 sop hms87c1202a d 16 pdip hms87c1102a 16 sop hms87c1102a d
4 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 2. block diagram alu accumulator stack pointer interrupt controller data memory 8-bit converter a/d 8-bit counter timer/ program memory data table pc 8-bit basic timer interval watch-dog timer instruction ra rb rc buzzer ? driver psw system controller timing generator system clock controller clock generator reset x in x out ra0 / ec0 ra1 / an1 ra2 / an2 ra3 / an3 ra4 / an4 ra5 / an5 ra6 / an6 ra7 / an7 rb0 / an0 / av ref rb1 / buz ? rb2 / int0 rb3 / int1 ? rb4 / cmp0 / pwm0 rc0 ? rc1 ? v dd v ss power supply decoder high pwm speed rd rd0 ?, ? rd1 ?, ? rd2 ?, ? rd3 ?, ? ? these pins are not available in hms87c1204(2)a. ? these pins are not available in hms87c1104(2)a. note
hms87c130xa/120xa/110xa apr. 2001 ver1.0 5 3. pin assignment ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 rc1 rc0 v ss reset x out x in an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd rd0 rd1 24 skdip 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 11 12 rd3 rd2 14 13 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 rc1 rc0 v ss reset x out x in an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd an0 / av ref / rb0 buz / rb1 int0 / rb2 int1 / rb3 pwm0 / comp0 / rb4 24 sop 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 11 12 rd3 rd2 14 13 an0 / av ref / rb0 buz / rb1 int0 / rb2 int1 / rb3 pwm0 / comp0 / rb4 rd1 rd0 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 rc1 rc0 v ss reset x out x in an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd 20 pdip 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 rc1 rc0 v ss reset x out x in an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd an0 / av ref / rb0 buz / rb1 int0 / rb2 int1 / rb3 pwm0 / comp0 / rb4 20 sop 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 an0 / av ref / rb0 buz / rb1 int0 / rb2 int1 / rb3 pwm0 / comp0 / rb4 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 v ss reset x out x in an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd 16 pdip 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 v ss reset x out x in an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd an0 / av ref / rb0 int0 / rb2 pwm0 / comp0 / rb4 16 sop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 an0 / av ref / rb0 int0 / rb2 pwm0 / comp0 / rb4 hms87c1304(2)a sk hms87c1304(2)a d hms87c1204(2)a hms87c1204(2)a d hms87c1104(2)a hms87c1104(2)a d
6 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 4. package diagram 1.265 0.045 typ 0.100 typ 0.300 0.300 0 . 0 1 4 0 ~ 15 max 0.180 min 0.015 0.120 0.292 0.398 0.614 0.104 0.0138 typ 0.050 0.004 0.009 0 ~ 8 0.016 24 skdip 24 sop unit: inch max min 1.160 0.021 0.140 0.065 0 . 0 0 8 0.250 0.419 0.299 0.593 0.093 0.019 0.042 0.0125 0.0118 0.015
hms87c130xa/120xa/110xa apr. 2001 ver1.0 7 1.043 0.050 typ 0.100 typ 0.300 0.270 0 . 0 1 4 0 ~ 15 max 0.180 min 0.015 0.120 0.291 0.398 0.5118 0.104 0.013 typ 0.050 0.004 0.0091 0 ~ 8 0.016 20 pdip 20 sop unit: inch max min 1.010 0.021 0.140 0.065 0 . 0 0 8 0.245 0.419 0.299 0.4961 0.093 0.020 0.042 0.0125 0.0118 0.015
8 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 0.765 0.050 typ 0.100 typ 0.300 0.260 0 . 0 1 4 0 ~ 15 max 0.180 min 0.015 0.120 0.292 0.398 0.412 0.104 0.014 typ 0.050 0.004 0.0091 0 ~ 8 0.016 16 pdip 16 sop unit: inch max min 0.745 0.022 0.140 0.065 0 . 0 0 8 0.240 0.416 0.299 0.402 0.094 0.019 0.040 0.0125 0.0118 0.015
hms87c130xa/120xa/110xa apr. 2001 ver1.0 9 5. pin function v dd : supply voltage. v ss : circuit ground. reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. ra0~ra7 : ra is an 8-bit, cmos, bidirectional i/o port. ra pins can be used as outputs or inputs according to 1 or 0 written the their port direction register(raio). in addition, ra serves the functions of the various special features in table 5-1. rb0~rb4 : rb is an 8-bit, cmos, bidirectional i/o port. rb pins can be used as outputs or inputs according to 1 or 0 written the their port direction register(rbio). rb serves the functions of the various following special features in table 5-2. rc0, rc1 : rc is a 2-bit, cmos, bidirectional i/o port. rc pins can be used as outputs or inputs according to 1 or 0 written the their port direction register(rcio). and these pins are not available in hms87c1104(2)a. rd0~rd3 : rd is a 4-bit, cmos, bidirectional i/o port. rc pins can be used as outputs or inputs according to 1 or 0 written the their port direction register(rdio). and these pins are not available in hms87c1204(2)a and hms87c1104(2)a. port pin alternate function ra0 ra1 ra2 ra3 ra4 ra5 ra6 ra7 ec0 ( event counter input source ) an1 ( analog input port 1 ) an2 ( analog input port 2 ) an3 ( analog input port 3 ) an4 ( analog input port 4 ) an5 ( analog input port 5 ) an6 ( analog input port 6 ) an7 ( analog input port 7 ) table 5-1 ra port port pin alternate function rb0 rb1 1 rb2 rb3 1 rb4 1. these pins are not available in hms87c1104(2)a. an0 ( analog input port 0 ) av ref ( external analog reference pin ) buz ( buzzer driving output port ) int0 ( external interrupt input port 0 ) int1 ( external interrupt input port 1 ) pwm0 (pwm0 output) comp0 (timer1 compare output) table 5-2 rb port
10 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa pin name pin number in/out function 87c1304(2)a 87c1204(2)a 87c1104(2)a basic sencondary v dd 555 - supply voltage v ss 18 14 12 - circuit ground reset 17 13 11 i reset signal input x in 15 11 9 i x out 16 12 10 o ra0 (ec0) 21 17 13 i/o (input) 8-bit general i/o ports external event counter input 0 ra1 (an1) 22 18 14 i/o (input) analog input port 1 ra2 (an2) 23 19 15 i/o (input) analog input port 2 ra3 (an3) 24 20 16 i/o (input) analog input port 3 ra4 (an4) 1 1 1 i/o (input) analog input port 4 ra5 (an5) 2 2 2 i/o (input) analog input port 5 ra6 (an6) 3 3 3 i/o (input) analog input port 6 ra7 (an7) 4 4 4 i/o (input) analog input port 7 rb0 (avref/an0) 8 6 6 i/o (input) 5-bit general i/o ports analog input port 0 / analog reference rb1 (buz) 9 7 i/o (input) buzzer driving output rb2 (int0) 10 8 i/o (input) external interrupt input 0 rb3 (int1) 11 9 i/o (output) external interrupt input 1 rb4 (pwm0/ comp0) 12 10 i/o (output/ output) pwm0 output or timer1 compare output rc0 19 15 i/o 2-bit general i/o ports rc1 20 16 i/o rd0 6 i/o 4-bit general i/o ports rd1 7 i/o rd2 13 i/o rd3 14 i/o table 5-3 pin description
hms87c130xa/120xa/110xa apr. 2001 ver1.0 11 6. port structures ? reset ? xin, xout v ss internal reset v ss xout xin stop to system clk v dd v ss xout xin stop to system clk v dd internal capacitor 6 pf crystal or ceramic rc oscillation (refer to configuration area)
12 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa ? ra0/ec0 ? ra1/an1 ~ ra7/an7 data bus data bus data bus data reg. direction reg. read ec0 schmitt trigger open drain v dd v ss data bus data bus data bus read to a/d converter analog input mode (ansel7 ~ 1) analog ch. selection (adcm.4 ~ 2) data reg. direction reg.
hms87c130xa/120xa/110xa apr. 2001 ver1.0 13 ? rb0 / an0 / avref ? rb1/buz, rb4/pwm0/comp0 note: rb1/buz pin is not available in hms87c1104(2)a. v dd v ss data bus data bus data bus read to a/d converter analog input mode (ansel0) analog ch0 selection (adcm.4 ~ 2) avrefs avrefs internal v dd 0 1 to vref of a/d data reg. direction reg. v dd v ss data bus data bus data bus read 0 1 function select pwm/comp buz data reg. direction reg.
14 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa ? rb2/int0, rb3/int1 note: rb3/int1 pin is not available in hms87c1104(2)a . ? rc0, rd2, rd3 note: rc0, rd2, rd3 pins are not available in hms87c1104(2)a note: rd2, rd3 pins are not available in hms87c1204(2) v dd v ss data bus data bus data bus read function select pull-up select int0, int1 schmitt trigger weak pull-up data reg. direction reg. open drain data bus data bus data bus data reg. direction reg. read
hms87c130xa/120xa/110xa apr. 2001 ver1.0 15 ? rc1 ? rd0, rd1 v dd v ss data bus data bus data bus read data reg. direction reg. open drain v dd v ss data bus data bus data bus read pull-up select weak pull-up data reg. direction reg.
16 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 7. electrical characteristics 7.1 absolute maximum ratings supply voltage ........................................... -0.3 to +6.0 v storage temperature ................................-40 to +125 c voltage on any pin with respect to ground (v ss ) ............................................................... -0.3 to v dd +0.3 maximum current out of v ss pin ........................200 ma maximum current into v dd pin ..........................150 ma maximum current sunk by (i ol per i/o pin) ........25 ma maximum output current sourced by (i oh per i/o pin) ...............................................................................15 ma maximum current ( s i ol ) ....................................150 ma maximum current ( s i oh ).................................... 100 ma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional op- eration of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 recommended operating conditions 7.3 a/d converter characteristics (t a =25 c, v ss =0v, v dd =5.12v @ f xin =8mhz, v dd =3.072v @ f xin =4mhz) parameter symbol condition specifications unit min. max. supply voltage v dd f xin =8mhz 4.5 5.5 v f xin =4.2mhz 2.0 5.5 v operating frequency f xin v dd =4.5~5.5v 18mhz v dd =2.0~5.5v 14.2mhz operating temperature t opr -20 85 c parameter symbol condition specifications unit min. typ. max. analog input voltage range v ain avrefs=0 v ss - v dd v avrefs=1 v ss - v ref analog power supply input voltage range v ref v dd =5v 3- v dd v v dd =3v 2.4 - v dd v overall accuracy n acc - 1.0 1.5 lsb non-linearity error n nle - 1.0 1.5 lsb differential non-linearity error n dnle - 1.0 1.5 lsb zero offset error n zoe - 0.5 1.5 lsb full scale error n fse - 0.25 0.5 lsb gain error n nle - 1.0 1.5 lsb conversion time t conv f xin =8mhz --10 m s f xin =4mhz --20 av ref input current i ref avrefs=1 - 0.5 1.0 ma
hms87c130xa/120xa/110xa apr. 2001 ver1.0 17 7.4 dc electrical characteristics (t a =-20~85 c, v dd =2.0~5.5v , v ss =0v) , parameter symbol pin condition specifications unit min. typ. max. input high voltage v ih1 reset 0.8 v dd - v dd v v ih2 x in , hysteresis input 1 0.8 v dd - v dd v ih3 normal input 0.7 v dd - v dd input low voltage v il1 reset 0- 0.2 v dd v v il2 x in , hysteresis input 1 0- 0.2 v dd v il3 normal input 0 - 0.3 v dd output high voltage v oh all output port v dd =5v, i oh =-5ma v dd -1 --v output low voltage v ol all output port v dd =5v, i ol =10ma - -1v input pull-up current 2 i p rb2, rb3, rd0, rd1 v dd =5v -450 -380 -300 m a input high leakage current i ih1 all pins (except x in )v dd =5v --5 m a i ih2 x in v dd =5v --15 m a input low leakage current i il1 all pins (except x in )v dd =5v -5 - - m a i il2 x in v dd =5v -15 - - m a hysteresis | v t | hysteresis input 1 v dd =5v 0.5 - - v pfd voltage v pfd1 v dd pfd level = 0, v dd =5v 2.0 2.5 3.0 v v pfd2 v dd pfd level = 1, v dd =3v 1.5 1.7 1.9 internal rc wdt period t rcwdt v dd =5.0v, f xin =8mhz 60 200 m s v dd =3.0v, f xin =4mhz 150 300 operating current 3 i dd v dd v dd =5.5v, f xin =8mhz -25 ma v dd =3.0v, f xin =4mhz -12 wake-up timer mode current i wkup v dd v dd =5.5v, f xin =8mhz -0.10.5 ma v dd =3.0v, f xin =4mhz - 0.03 0.1 rcwdt mode current at stop mode i rcwdt v dd v dd =5.5v --50 m a v dd =3.0v --30 stop mode current i stop v dd v dd =5.5v, f xin =8mhz -0.71.6 m a v dd =3.0v, f xin =4mhz -0.20.8 external rc oscillator frequency f rc x out v dd =5v, r=10k w , c=20pf 35 mhz v dd =5v, r=10k w 59 1. hysteresis input: ra0, rb2, rb3 2. this parameter is valid when the bit pupselx is selected and set the input mode or interrupt input function. 3. this value is measured under nop instruction execution.
18 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 7.5 ac characteristics (t a =-20~+85 c, v dd =5v 10% , v ss =0v) figure 7-1 timing chart parameter symbol pins specifications unit min. typ. max. operating frequency f cp x in 1-8mhz external clock pulse width t cpw x in 80 - - ns external clock transition time t rcp, t fcp x in - - 20 ns oscillation stabilizing time t st x in , x out --20ms external input pulse width t epw int0, int1, ec0 2 - - t sys reset input width t rst reset 8- - t sys t rcp t fcp x in int0, int1 0.5v v dd -0.5v 0.2v dd reset 0.2v dd 0.8v dd ec0 t rst t epw t epw 1/f cp t cpw t cpw t sys
hms87c130xa/120xa/110xa apr. 2001 ver1.0 19 7.6 typical characteristics this graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. in some graphs or tables the data presented are out- side specified operating range (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation ta= 25 c ta=25 c i dd - v dd 4 3 2 1 0 (ma) i dd 23 45 6 v dd (v) normal operation (nop) 8 6 4 2 0 (mhz) f xin 23 45 6 v dd (v) operating area f xin = 8mhz 4mhz 10 i wkup - v dd 2.0 1.5 1.0 0.5 0 (ma) i dd 23 45 6 v dd (v) wake-up timer mode i rcwdt - v dd 20 15 10 5 0 ( m a) i dd 23 45 6 v dd (v) rc-wdt in stop mode ta=25 c f xin = 8mhz 4mhz ta=25 c i stop - v dd 2.0 1.5 1.0 0.5 0 ( m a) i dd 23 45 6 v dd (v) stop mode f xin = 8mhz -25 c 85 c 25 c t rcwdt = 180us
20 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa i ol - v ol , v dd =5v 40 30 20 10 0 (ma) i ol v ol (v) i oh - v oh , v dd =5v -20 -15 -10 -5 0 (ma) i oh 23 456 v oh (v) 0.5 1 1.5 2 2.5 f xin =4mhz v dd - v ih1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) v dd - v ih2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) ta=25 c f xin =4mhz ta=25 c 1 x in , reset hysteresis input -25 c 85 c 25 c -25 c 85 c 25 c v dd - v ih3 4 3 2 1 0 (v) v ih3 23 45 6 v dd (v) f xin =4mhz ta=25 c normal input f xin =4mhz v dd - v il1 4 3 2 1 0 (v) v il1 23 45 6 v dd (v) v dd - v il2 4 3 2 1 0 (v) v il2 23 45 6 v dd (v) ta=25 c f xin =4mhz ta=25 c 1 x in , reset hysteresis input v dd - v il3 4 3 2 1 0 (v) v il3 23 45 6 v dd (v) f xin =4mhz ta=25 c normal input
hms87c130xa/120xa/110xa apr. 2001 ver1.0 21 with external capacitor without external capcitor r ext c ext f osc @ 5v,25 c f osc @ 3v,25 c f osc @ 5v,25 c f osc @ 3v,25 c 10k w 10pf 4.9mhz 3.94mhz 7.29mhz 5.1mhz 20pf 3.35mhz 2.72mhz 40pf 2.12mhz 1.74mhz 30k w 10pf 1.81mhz 1.57mhz 2.96mhz 2.37mhz 20pf 1.21mhz 1.04mhz 40pf 0.75mhz 0.65mhz 50k w 10pf 1.11mhz 0.98mhz 1.85mhz 1.55mhz 20pf 0.74mhz 0.65mhz 40pf 0.46mhz 0.40mhz table 7-1 rc oscillation frequencies (with c ext and without c ext)
22 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 8. memory organization the hms87c1x0xa has separate address spaces for pro- gram memory and data memory. program memory can only be read, not written to. it can be up to 2k/4k bytes of program memory. data memory can be read and written to up to 128 bytes including the stack area. 8.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is an 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. stack pointer : the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 00 h to 7f h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initial- ization routine. normally, the initial value of 7f h is used. note: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #07fh txsp ; sp ? 7f h program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset rou- tine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 8-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. a accumulator x register y register stack pointer program counter program status word x y sp pcl pch psw two 8-bit registers can be used as a ya 16-bit register y a y a sp 0 stack address (000 h ~ 07f h ) 15 0 87 hardware fixed
hms87c130xa/120xa/110xa apr. 2001 ver1.0 23 figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to 0. this flag immedi- ately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v - b h i z c msb lsb reset value: 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands
24 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but these devices have 4k/2k bytes program memory space only physically implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-4, shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 8-5. as shown in figure 8-4, each area is assigned a fixed loca- tion in program memory. program memory area contains the user program. figure 8-4 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-6. example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to loca- tion 0fffa h . the interrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for external interrupt 0, etc. as for the area from 0ff00 h to 0ffff h , if any area of them is not going to be used, its service location is avail- able as general purpose program memory. figure 8-5 interrupt vector area program memory tcall area interrupt vector area f000h feffh ff00h ffc0h ffdfh ffe0h ffffh pcall area f800h hms87c1302a HMS87C1304A lda #5 tcall 0fh ; 1byte instruction :; instead of 3 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe - - - basic interval interrupt vector area a/d converter interrupt vector area - - - timer/counter 1 interrupt vector area timer/counter 0 interrupt vector area external interrupt 0 vector area - reset vector area external interrupt 1 vector area - watchdog timer interrupt vector area - means reserved area. note:
hms87c130xa/120xa/110xa apr. 2001 ver1.0 25 figure 8-6 pcall and tcall memory area pcall ? ? ? ? rel 4f35 pcall 35h tcall ? ? ? ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35h 0ff00h 0ffffh 11111111 11010110 01001010 pc: f h f h d h 6 h 4a ~ ~ ~ ~ 25 0ffd6h 0ff00h 0ffffh f1 next 0ffd7h ? 0f125h reverse
26 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa example: the usage software example of vector address and the initialize part. org 0ffe0h dw not_used ; (0ffe0) dw not_used ; (0ffe2) dw not_used ; (0ffe4) dw bit_int ; (0ffe6) basic interval timer dw wdt_int ; (0ffe8) watchdog timer dw ad_int ; (0ffea) a/d dw not_used ; (0ffec) dw not_used ; (0ffee) dw not_used ; (0fff0) dw not_used ; (0fff2) dw tmr1_int ; (0fff4) timer-1 dw tmr0_int ; (0fff6) timer-0 dw int1 ; (0fff8) int.1 dw int0 ; (0fffa) int.0 dw not_used ; (0fffc) dw reset ; (0fffe) reset org 0f000h ;******************************************** ; main program * ;******************************************* ; reset: di ;disable all interrupts ldx #0 ram_clr: lda #0 ;ram clear(!0000h->!007fh) sta {x}+ cmpx #080h bne ram_clr ; ldx #07fh ;stack pointer initialize txsp ; call initial ; ; ldm ra, #0 ;normal port a ldm raio,#1000_0010b ;normal port direction ldm rb, #0 ;normal port b ldm rbio,#0000_0010b ;normal port direction : : ldm pfdr,#0 ;enable power fail detector : :
hms87c130xa/120xa/110xa apr. 2001 ver1.0 27 8.3 data memory figure 8-7 shows the internal data memory space availa- ble. data memory is divided into two groups, a user ram (including stack) and control registers. figure 8-7 data memory map user memory the hms87c1x0xa has 128 8 bits for the user memory (ram). control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruction. use byte manipulation instruction. example; to write at ckctlr ldm ckctlr,#09h ;divide ratio ? 16 user memory control registers 0000h 00bfh 00c0h 00ffh page0 (including stack) 007fh 0080h address symbol r/w reset value addressing mode 0c0h 0c1h 0c2h 0c3h 0c4h 0c5h 0c6h 0c7h 0cah 0cbh 0cch ra raio rb rbio rc rcio rd rdio rafunc rbfunc pupsel r/w w r/w w r/w w r/w w w w w undefined 0000_0000 undefined 0000_0000 undefined ----_--00 undefined ----_0000 0000_0000 0000_0000 ----_0000 byte, bit 1 byte 2 byte, bit byte byte, bit byte byte, bit byte byte byte byte 0d0h 0d1h 0d1h 0d1h 0d2h 0d3h 0d3h 0d4h 0d4h 0d4h 0d5h tm0 t0 tdr0 cdr0 tm1 tdr1 t1ppr t1 cdr1 t1pdr pwm0hr r/w r w r r/w w w r r r/w w --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte 0deh bur w 1111_1111 byte 0e2h 0e3h 0e4h 0e5h 0e6h 0eah 0ebh 0ech 0ech 0edh 0edh 0efh ienh ienl irqh irql ieds adcm adcr bitr ckctlr wdtr wdtr pfdr r/w r/w r/w r/w r/w r/w r r w r w r/w 0000_---- 000-_---- 0000_---- 000-_---- ----_0000 --00_0001 undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_0100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit table 8-1 control registers 1. byte, bit means that register can be addressed by not only bit but byte manipulation instruction. 2. byte means that register can be addressed by only byte manipulation instruction. on the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit.
28 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa note: several names are given at same address. refer to below table. stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. addr. when read when write timer mode capture mode pwm mode timer mode pwm mode d1h t0 cdr0 - tdr0 - d3h - tdr1 t1ppr d4h t1 cdr1 t1pdr - t1pdr ech bitr ckctlr table 8-2 various register name in same address
hms87c130xa/120xa/110xa apr. 2001 ver1.0 29 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0h ra ra port data register c1h raio ra port direction register c2h rb rb port data register c3h rbio rb port direction register c4h rc rc port data register c5h rcio rc port direction register c6h rd rd port data register c7h rdio rd port direction register cah rafunc ansel7 ansel6 ansel5 ansel4 ansel3 ansel2 ansel1 ansel0 cbh rbfunc tmr2ov ec1i pwm1o pwm0o int1i int0i buzo avrefs cch pupsel - - - - pupsel3 pupsel2 pupsel1 pupsel0 d0h tm0 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st d1h t0/tdr0/ cdr0 timer0 register / timer0 data register / capture0 data register d2h tm1 pol 16bit pwm0e cap1 t1ck1 t1ck0 t1cn t1st d3h tdr1/ t1ppr timer1 data register / pwm0 period register d4h t1/cdr1/ t1pdr timer1 register / capture1 data register / pwm0 duty register d5h pwm0hr pwm0 high register deh bur buck1 buck0 bur5 bur4 bur3 bur2 bur1 bur0 e2hienh int0eint1et0et1e---- e3hienl adewdtebite----- e4hirqhint0ifint1ift0ift1if---- e5hirql adifwdtifbitif----- e6hieds ----ied1hied1lied0hied0l eah adcm - - aden ads2 ads1 ads0 adst adsf ebh adcr adc result data register ech bitr 1 basic interval timer data register ech ckctlr 1 - wakeup rcwdt wdton btcl bts2 bts1 bts0 edh wdtr wdtcl 7-bit watchdog counter register efh pfdr 2 ----pfdoprpfdispfdmpfds table 8-3 control registers of hms87c1x0xa these registers of shaded area can not be accessed by bit manipulation instruction as set1, clr1, but should be accessed by register operation instruction as ldm dp,#imm. 1.the register bitr and ckctlr are located at same address. address ech is read as bitr, written to ckctlr. 2.the register pfdr only be implemented on devices, not on in-circuit emulator.
30 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 8.4 addressing mode the hms87c1x0xa uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: 0435 adc #35h e45535 ldm 35h,#55h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; c535 lda 35h ;a ? ram[35h] (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data, i.e. second byte(operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a ? rom[0f035h] 35 a+35h+c ? a 04 memory e4 0f100 h data ? 55h ~ ~ ~ ~ data 0035 h 35 0f102 h 55 0f101 h ? data 35 0035 h 0f551 h data ? a ? ~ ~ ~ ~ c5 0f550 h 07 0f100 h ~ ~ ~ ~ data 0f035 h f0 0f102 h 35 0f101 h ? a+data+c ? a address: 0f035
hms87c130xa/120xa/110xa apr. 2001 ver1.0 31 the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h . 983500 inc !0035h ;a ? ram[035h] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; x=015 h c645 lda 45h+x 98 0f100 h ~ ~ ~ ~ data 0035 h 00 0f102 h 35 0f101 h ? data+1 ? data address: 0035 data d4 15 h 0f550 h data ? a ? ~ ~ ~ ~ data db 35 h data ? a ? ~ ~ ~ ~ 36h ? x data 45 5a h 0f551 h data ? a ? ~ ~ ~ ~ c6 0f550 h 45h+15h=5ah
32 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory. this addressing mode can specify mem- ory in whole area. example; y=55 h d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data(or pair memory) by operand. also index can be used with index register x,y. jmp, call example; 3f35 jmp [35h] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; x=10 h 1625 adc [25h+x] d5 0f100 h data ? a ~ ~ ~ ~ data 0fa55 h 0fa00h+55h=0fa55h fa 0f102 h 00 0f101 h ? 0a 35 h jump to address 0f30a h ~ ~ ~ ~ 35 0fa00 h f3 36 h ? 3f 0f30a h next ~ ~ ~ ~ 05 35 h 0f405 h ~ ~ ~ ~ 25 0fa00 h f4 36 h 16 0f405 h data ~ ~ ~ ~ a + data + c ? a 25 + x(10) = 35 h ?
hms87c130xa/120xa/110xa apr. 2001 ver1.0 33 y indexed indirect ? ? ? ? [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; y=10 h 1725 adc [25h]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; 1f25f0 jmp [!0f025h] 05 25 h 0f705 h + y(10) = 0f715 h ~ ~ ~ ~ 25 0fa00 h f7 26 h ? 17 0f715 h data ~ ~ ~ ~ a + data + c ? a 25 0f025 h jump to ~ ~ ~ ~ f0 0fa00 h f8 0f026 h ? 25 0f825 h next ~ ~ ~ ~ 1f program memory address 0f80a h
34 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 9. i/o ports the hms87c1x0xa has four ports, ra, rb, rc and rd. these ports pins may be multiplexed with an alternate function for the peripheral features on the device. in gen- eral, when a initial reset state, all ports are used as a general purpose input port. all pins have data direction registers which can set these ports as output or input. an 1 in the port direction regis- ter defines the corresponding port pin as output. converse- ly, write 0 to the corresponding bit to specify as an input pin. for example, to use the even numbered bit of ra as output ports and the odd numbered bits as input ports, write 55 h to address c1 h (ra direction register) during initial setting as shown in figure 9-1. reading data register reads the status of the pins whereas writing to it will write to the port latch. figure 9-1 example of port i/o assignment 9.1 ra and raio registers ra is an 8-bit bidirectional i/o port (address c0 h ). each port can be set individually as input and output through the raio register (address c1 h ). ra1~ra7 ports are multiplexed with analog input port (an1~an7) and ra0 port is multiplexed with event counter input port (ec0) . figure 9-2 registers of port ra the control register rafunc (address ca h ) controls to select alternate function. after reset, this value is 0, port may be used as general i/o ports. to select alternate func- tion such as analog input or external event counter input, write 1 to the corresponding bit of rafunc.regardless of the direction register raio, rafunc is selected to use as alternate functions, port pin can be used as a correspond- ing alternate features (ra0/ec0 is controlled by rb- func) i: input port write 55h to port ra direction register 0 1 0 1 0 1 0 1 i o i o i o i o ra data rb data ra direction rb direction c0h c1h c2h c3h 76543210 bit 76543210port o: output port ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 input / output data 0 : input port 1 : output port direction select ra data register ra address : c0h reset value : undefined ra direction register raio address : c1h reset value : 00000000 ansel0 ra function selection register rafunc address : cah reset value : 00000000 ansel7 ansel1 ansel2 ansel3 ansel4 ansel5 ansel6 0 : rb0 1 : an0 0 : ra1 1 : an1 0 : ra2 1 : an2 0 : ra3 1 : an3 0 : ra4 1 : an4 0 : ra5 1 : an5 0 : ra6 1 : an6 0 : ra7 1 : an7 port rafunc.7~0 description ra7/an7 0 ra7 (normal i/o port) 1 an7 (ads2~0=111) ra6/an6 0 ra6 (normal i/o port) 1 an6 (ads2~0=110) ra5/an5 0 ra5 (normal i/o port) 1 an5 (ads2~0=101) ra4/an4 0 ra4 (normal i/o port) 1 an4 (ads2~0=100) ra3/an3 0 ra3 (normal i/o port) 1 an3 (ads2~0=011) ra2/an2 0 ra2 (normal i/o port) 1 an2 (ads2~0=010) ra1/an1 0 ra1 (normal i/o port) 1 an1 (ads2~0=001) ra0/ec0 1 1. this port is not an analog input port, but event counter clock source input port. ec0 is controlled by setting tock2~0 = 111. the bit rafunc.0 (ansel0) controls the rb0/an0/avref port (refer to port rb). ra0 (normal i/o port) ec0 (t0ck2~0=111)
hms87c130xa/120xa/110xa apr. 2001 ver1.0 35 9.2 rb and rbio registers rb is a 5-bit bidirectional i/o port (address c2 h ). each pin can be set individually as input and output through the rbio register (address c3 h ). in addition, port rb is mul- tiplexed with various special features. the control register rbfunc (address cb h ) controls to select alternate func- tion. after reset, this value is 0, port may be used as gen- eral i/o ports. to select alternate function such as external interrupt or timer compare output, write 1 to the corre- sponding bit of rbfunc. regardless of the direction register rbio, rbfunc is se- lected to use as alternate functions, port pin can be used as a corresponding alternate features. and rb2/int0, rb3/int1 have a function of pull-up transistor by setting the pupsel0 and pupsel1 of pupsel register. figure 9-3 registers of port rb - rb4 rb3 rb2 rb1 rb0 input / output data 0 : input port 1 : output port direction select rb data register rb address : c2h reset value : undefined rb direction register rbio address : c3h reset value : ---00000 avrefs rb function selection register rbfunc address : cbh reset value : ---00000 buzo int0i int1i pwm0o 0 : rb0 when ansel0 = 0 1 : av ref 0 : rb1 1 : buz output 0 : rb4 1 : pwm0 output or 0 : rb2 1 : int0 0 : rb3 1 : int1 pupsel0 pull-up selection register pupsel address : cch reset value : ----0000 - pupsel1 - - - 0 : no pull-up 1 : with pull-up 0 : no pull-up 1 : with pull-up ied0l interrupt edge selection register ieds address : e6h reset value : ----0000 ied0h ied1l ied1h external interrupt edge select int0 int1 00 : normal i/o port 01 : falling (1-to-0 transition) 10 : rising (0-to-1 transition) 11 : both (rising & falling) compare output rb0 / int0 pull-up rb1 / int1 pull-up an0 when ansel0 = 1 - - - - - - - - - - - - --
36 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 9.3 rc and rcio registers rc is a 2-bit bidirectional i/o port (address c4 h ). each pin can be set individually as input and output through the rcio register (address c5 h ). figure 9-4 registers of port rc port rbfunc.4~0 description rb4/ pwm0/ comp0 0 rb4 (normal i/o port) 1 pwm0 output / timer1 compare output rb3/int1 0 rb3 (normal i/o port) 1 external interrupt input 1 rb2/int0 0 rb2 (normal i/o port) 1 external interrupt input 0 rb1/buz 0 rb1 (normal i/o port) 1 buzzer output rb0/an0/ av ref 0 1 1. when ansel0 = 0, this port is defined for normal i/o port (rb0). when ansel0 = 1 and ads2~0 = 000, this port can be used analog input port (an0). rb0 (normal i/o port)/ an0 (ansel0=1) 1 2 2. when this bit set to 1, this port defined for av ref , so it can not be used analog input port an0 and normal i/o port rb0. external analog reference voltage - rc1 rc0 input / output data 0 : input port 1 : output port direction select rc data register rc address : c4h reset value : undefined rc direction register rcio address : c5h reset value : ------00 - ---- ------
hms87c130xa/120xa/110xa apr. 2001 ver1.0 37 9.4 rd and rdio registers rd is a 4-bit bidirectional i/o port (address c6 h ). each pin can be set individually as input and output through the rdio register (address c7 h ) and rd0, rd1 have a function of pull-up transistor by set- ting the pupsel2 and pupsel3 of pupsel register. . figure 9-5 registers of port rd rd2 rd1 rd0 input / output data 0 : input port 1 : output port direction select rd data register rd address : c6h reset value : undefined rd direction register rdio address : c7h reset value : -----0000 rd3 ---- - pull-up selection register pupsel address : cch reset value : ----0000 - - - - - 0 : no pull-up 1 : with pull-up 0 : no pull-up 1 : with pull-up rd0 pull-up rd1 pull-up pupsel2 pupsel3 ----
38 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 10. clock generator the clock generator produces the basic clock pulses which provide the system clock to be supplied to the cpu and pe- ripheral hardware. the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator connected to the xin and xout pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the xin pin and open the xout pin. figure 10-1 block diagram of clock pulse generator 10.1 oscillation circuit x in and x out are the input and output, respectively, a in- verting amplifier which can be set for use as an on-chip os- cillator, as shown in figure 10-2. figure 10-2 oscillator connections to drive the device from an external clock source, xout should be left unconnected while xin is driven as shown in figure 10-3. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. figure 10-3 external clock connections note: when using a system clock oscillator, carry out wir- ing in the broken line area in figure 10-2 to prevent any effects from wiring capacities. - minimize the wiring length. - do not allow wiring to intersect with other signal conductors. - do not allow wiring to come near changing high current. - set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. - do not fetch signals from the oscillator. in addition, the hms87c1x0xa has an ability for the ex- ternal rc oscillated operation. it offers additional cost sav- ings for timing insensitive applications . the rc internal system clock prescaler clock pulse ? 1 peripheral clock ? 2 ? 4 ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 generator ? 2048 stop wakeup f xin oscillation circuit x out x in vss c1 c2 recommended: c1, c2 = 30pf 10pf for crystals r1 r1 = 1m w x out x in vss open external clock source
hms87c130xa/120xa/110xa apr. 2001 ver1.0 39 oscillator frequency is a function of the supply voltage, the external resistor (r ext ) and capacitor (c ext ) values, and the operating temperature. the user needs to take into account variation due to toler- ance of external r and c components used. figure 10-4 shows how the rc combination is connected to the hms87c1x0xa. figure 10-4 rc oscillator connections external capacitor (c ext ) can be omitted for more cost saving. however, the characteristics of external r only os- cillation are more variable than external rc oscillation. figure 10-5 r oscillator connections the oscillator frequency, divided by 4, is output from the xout pin, and can be used for test purpose or to synchroze other logic. to set the rc oscillation, it should be programmed rcopt bit to "1" to config (707f h ). ( refer to section "20.1". ) x out x in vdd c ext f xin ? 4 r ext cint ? 6pf x out x in v dd f xin ? 4 r ext c int ? 6pf
40 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 11. basic interval timer the hms87c1x0xa has one 8-bit basic interval timer that is free-run, can not stop. block diagram is shown in figure 11-1.the 8-bit basic interval timer register (bitr) is increased every internal count pulse which is divided by prescaler. since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. as the count overflows from ff h to 00 h , this overflow causes to generate the basic interval timer interrupt. the bitf is interrupt request flag of basic interval timer. when write 1 to bit btcl of ckctlr, bitr register is cleared to 0 and restart to count-up. the bit btcl be- comes 0 after one machine cycle by hardware. if the stop instruction executed after writing 1 to bit wakeup of ckctlr, it goes into the wake-up timer mode. in this mode, all of the block is halted except the os- cillator, prescaler (only fxin ? 2048) and timer0. if the stop instruction executed after writing 1 to bit rcwdt of ckctlr, it goes into the internal rc oscillat- ed watchdog timer mode. in this mode, all of the block is halted except the internal rc oscillator, basic interval timer and watchdog timer. more detail informations are explained in power saving function. the bit wdton de- cides watchdog timer or the normal 7-bit timer note: all control bits of basic interval timer are in ckctlr register which is located at same address of bitr (address ec h ). address ec h is read as bitr, writ- ten to ckctlr. therefore, the ckctlr can not be accessed by bit manipulation instruction. . figure 11-1 block diagram of basic interval timer figure 11-2 ckctlr: clock control register ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 0 1 mux 8 3 f xin bitr (8bit) bitif bts[2:0] internal rc osc basic interval timer interrupt btcl clear to watchdog timer stop wakeup rcwdt clock control register ckctlr address : ech reset value : -0010111 - wakeup rcwdt wdton btcl bts2 bts1 bts0 basic interval timer clock selection 000 : f xin ? 8 001 : f xin ? 16 100 : f xin ? 128 101 : f xin ? 256 110 : f xin ? 512 111 : f xin ? 1024 010 : f xin ? 32 011 : f xin ? 64 symbol function description wakeup 1 : enables wake-up timer 0 : disables wake-up timer rcwdt 1 : enables internal rc watchdog timer 0 : disables internal rc watchdog time wdton 1 : enables watchdog timer 0 : operates as a 7-bit timer btcl 1 : bitr is cleared and btcl becomes 0 automatically after one machine cycle, and bitr continue to count-up bit manipulation not available
hms87c130xa/120xa/110xa apr. 2001 ver1.0 41 12. timer / counter the hms87c1x0xa has two timer/counter registers. each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). timer 0 and timer 1 can be used either two 8-bit timer/ counter or the one 16-bit timer/counter by combining them. in the timer function, the register is increased every in- ternal clock input. thus, one can think of it as counting in- ternal clock input. since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in timer0. and timer1 can use the same clock source too. in addition, timer1 has more fast clock source (1/1 to 1/8). in the counter function, the register is increased in re- sponse to a 0-to-1 (rising edge) transition at its correspond- ing external input pin, ec0(timer 0). note: if changing the timer value or starting again, it should be stop the timer clock firstly, and then set timer register value. ex) ldm tm0,#00001100b ldm tdr,#7fh ldm tm0,#00010111b in addition the capture function, the register is increased in response external interrupt same with timer function. when external interrupt edge input, the count register is captured into capture data register cdrx. timer1 is shared with pwm function and compare output function it has seven operating modes: 8-bit timer/counter, 16- bit timer/counter, 8-bit capture, 16-bit capture, 8-bit compare output, 16-bit compare output and 10-bit pwm which are selected by bit in timer mode register tmx as shown in figure 12-1 and table 12-1. figure 12-1 timer mode register (tm0, tm1) timer 0 mode register tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st timer 1 mode register tm1 address : d2h reset value : 00000000 pol 16bit pwm0e cap1 t1ck1 t1ck0 t1cn t1st cap0 capture mode selection bit . 0 : disables capture 1 : enables capture t0cn continue control bit 0 : stop counting 1 : start counting continuously t0ck[2:0] input clock selection 000 : f xin ? 2, 100 : f xin ? 128 001 : f xin ? 4, 101 : f xin ? 512 010 : f xin ? 8, 110 : f xin ? 2048 011 : f xin ? 32, 111 : external event ( ec0 ) t0st start control bit 0 : stop counting 1 : start counting pol pwm output polarity 0 : duty active low 1 : duty active high t1ck[2:0] input clock selection 00 : f xin 10 : f xin ? 8 01 : f xin ? 2 11 : using the timer 0 clock 16bit 16-bit mode selection 0 : 8-bit mode 1 : 16-bit mode t1cn continue control bit 0 : stop counting 1 : start counting continuously pwm0e pwm enable bit 0 : disables pwm 1 : enables pwm t1st start control bit 0 : stop counting 1 : start counting cap1 capture mode selection bit . 0 : disables capture 1 : enables capture
42 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 12.1 8-bit timer/counter mode the hms87c1x0xa has four 8-bit timer/counters, tim- er 0 and timer 1 as shown in figure 12-2. the timer or counter function is selected by mode reg- isters tmx as shown in figure 12-1 and table 12-1. to use as an 8-bit timer/counter mode, bit cap0 of tm0 is cleared to 0 and bits 16bit of tm1 should be cleared to 0(table 12-1). figure 12-2 8-bit timer / counter mode 16bit cap0 cap1 pwme t0ck[2:0] t1ck[1:0] pwmo timer 0 timer1 0 0 0 0 xxx xx 0 8-bit timer 8-bit timer 0 0 1 0 111 xx 0 8-bit event counter 8-bit capture 0 1 0 0 xxx xx 1 8-bit capture 8-bit compare output 0 x 1 0 1 xxx xx 1 8-bit timer/counter 10-bit pwm 1 0 0 0 xxx 11 0 16-bit timer 1 0 0 0 111 11 0 16-bit event counter 1 1 x 0 xxx 11 0 16-bit capture 1 0 0 0 xxx 11 1 16-bit compare output table 12-1 operating modes of timer 0 and timer 1 1. x: the value 0 or 1 corresponding your operation. ? 1 ? 2 ? 8 tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st -- 0 xxxxx x 000 xxxx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 f xin ec0 edge detector mux mux 1 1 t0 (8-bit) tdr0 (8-bit) t0if clear comparator timer 0 interrupt t1 (8-bit) tdr1 (8-bit) t1if clear comparator timer 1 interrupt t0st 0 : stop 1 : start t1st 0 : stop 1 : start t0cn t1cn t0ck[2:0] t1ck[1:0] f/f comp0 pin ? 2048 x: the value 0 or 1 corresponding your operation.
hms87c130xa/120xa/110xa apr. 2001 ver1.0 43 these timers have each 8-bit count register and data regis- ter. the count register is increased by every internal or ex- ternal clock input. the internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by con- trol bits t0ck2, t0ck1 and t0ck0 of register tm0) and 1, 2, 8 (selected by control bits t1ck1 and t1ck0 of reg- ister tm1). in the timer 0, timer register t0 increases from 00 h until it matches tdr0 and then reset to 00 h . the match output of timer 0 generates timer 0 interrupt (latched in t0f bit). as tdrx and tx register are in same address, when reading it as a tx, written to tdrx. in counter function, the counter is increased every 0-to 1 (rising edge) transition of ec0 pin. in order to use counter function, the bit ra0 of the ra direction register raio is set to 0. the timer 0 can be used as a counter by pin ec0 input, but timer 1 can not. figure 12-3 counting example of timer data registers figure 12-4 timer count operation ~ ~ timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt occur interrupt interrupt period up- c ount ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 p cp = p cp x (n+1) timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt stop clear & start disable enable start & stop t1st t1cn control count up- co unt ~ ~ ~ ~ t1st = 0 t1st = 1 t1cn = 0 t1cn = 1
44 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 12.2 16-bit timer/counter mode the timer register is being run with 16 bits. a 16-bit timer/ counter register t0, t1 are increased from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match output generates timer 0 interrupt not timer 1 in- terrupt. the clock source of the timer 0 is selected either internal or external clock by bit t0ck2, t0ck1 and t0sl0. in 16-bit mode, the bits t1ck1,t1ck0 and 16bit of tm1 should be set to 1 respectively. figure 12-5 16-bit timer / counter mode 12.3 8-bit compare output (16-bit) the hms87c1x0xa has a function of timer compare output. to pulse out, the timer match can goes to port pin(comp0) as shown in figure 12-2 and figure 12-5. thus, pulse out is generated by the timer match. these op- eration is implemented to pin, rb4/comp0/pwm. this pin output the signal having a 50: 50 duty square wave, and output frequency is same as below equation. in this mode, the bit pwmo of rb function register (rb- func) should be set to 1, and the bit pwme of timer1 mode register (tm1) should be set to 0. in addition, 16-bit compare output mode is available, also. 12.4 8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode register tm0 (bit cap1 of timer mode register tm1 for timer 1) as shown in figure 12-6. as mentioned above, not only timer 0 but timer 1 can also be used as a capture mode. the timer/counter register is increased in response inter- nal or external input. this counting function is same with normal timer mode, and timer interrupt is generated when timer register t0 (t1) increases and matches tdr0 (tdr1). tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st -- 0 xxxxx x 10011 xx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 f xin ec0 edge detector mux 1 t1 (8-bit) tdr1 (8-bit) t0if clear comparator timer 0 interrupt t0 (8-bit) tdr0 (8-bit) t0st 0 : stop 1 : start t0cn t0ck[2:0] f/f comp0 pin ? 2048 x: the value 0 or 1 corresponding your operation. f comp oscillation frequency 2 prescaler value tdr 1 ) + ( -------------------------------------------------------------------------------- =
hms87c130xa/120xa/110xa apr. 2001 ver1.0 45 this timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of timer. for example, in figure 12-8, the pulse width of captured signal is wider than the timer data value (ff h ) over 2 times. when external interrupt is occurred, the captured value (13 h ) is more little than wanted value. it can be ob- tained correct value by counting the number of timer over- flow occurrence. timer/counter still does the above, but with the added fea- ture that a edge transition at external input intx pin causes the current value in the timer x register (t0,t1), to be cap- tured into registers cdrx (cdr0, cdr1), respectively. after captured, timer x register is cleared and restarts by hardware. it has three transition modes: falling edge, rising edge, both edge which are selected by interrupt edge selection register ieds (refer to external interrupt section). in ad- dition, the transition at intx pin generate an interrupt. note: the cdrx, tdrx and tx are in same address. in the capture mode, reading operation is read the cdrx, not tx because path is opened to the cdrx, and tdrx is only for writing operation. figure 12-6 8-bit capture mode ? 1 ? 2 ? 8 tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st -- 1 xxxxx x 001 xxxx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 f xin ec0 edge detector mux mux 1 1 t0 (8-bit) cdr0 (8-bit) t0if clear comparator timer 0 interrupt t0st 0 : stop 1 : start t0cn t1cn t0ck[2:0] t1ck[1:0] tdr0 (8-bit) int0if int 0 interrupt int0 t1 (8-bit) cdr1 (8-bit) t1if clear comparator timer 1 interrupt tdr1 (8-bit) int1if int 1 interrupt int1 t0st 0 : stop 1 : start ieds[1:0] ieds[3:2] capture capture ? 2048
46 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa figure 12-7 input capture operation figure 12-8 excess timer overflow in capture mode ~ ~ ext. int0 pin interrupt request t0 time up -c oun t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 capture (timer stop) clear & start interrupt interval period delay (int0f) ext. int0 pin interrupt request (int0f) this value is loaded to cdr0 interrupt interval period = ff h + 01 h + ff h +01 h + 13 h = 213 h ff h ff h ext. int0 pin interrupt request (int0f) 00 h 00 h interrupt request (t0f) t0 13 h
hms87c130xa/120xa/110xa apr. 2001 ver1.0 47 12.5 16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. the clock source of the timer 0 is selected either internal or external clock by bit t0ck2, t0ck1 and t0ck0. in 16-bit mode, the bits t1ck1,t1ck0 and 16bit of tm1 should be set to 1 respectively. figure 12-9 16-bit capture mode 12.6 pwm mode the hms87c1x0xa has a high speed pwm (pulse width modulation) functions which shared with timer1. in pwm mode, pin rb4/comp0/pwm0 outputs up to a 10-bit resolution pwm output. this pin should be config- ure as a pwm output by setting 1 bit pwm0o in rb- func register. the period of the pwm output is determined by the t1ppr (pwm0 period register) and pwm0hr[3:2] (bit3,2 of pwm0 high register) and the duty of the pwm output is determined by the t1pdr (pwm0 duty regis- ter) and pwm0hr[1:0] (bit1,0 of pwm0 high register). the user writes the lower 8-bit period value to the t1ppr and the higher 2-bit period value to the pwm0hr[3:2]. and writes duty value to the t1pdr and the pwm0hr[1:0] same way. the t1pdr is configure as a double buffering for glitch- less pwm output. in figure 12-10, the duty data is trans- ferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) pwm period = [pwm0hr[3:2]t1ppr] x source clock pwm duty = [pwm0hr[1:0]t1pdr] x source clock the relation of frequency and resolution is in inverse pro- portion. table 12-2 shows the relation of pwm frequency vs. resolution. tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st -- 1 xxxxx x 10 x 11 xx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 f xin ec0 edge detector mux 1 t0 + t1 (16-bit) tdr1 t0if clear comparator timer 0 interrupt t0st 0 : stop 1 : start t0cn t0ck[2:0] tdr0 int0if int 0 interrupt int0 ieds[1:0] capture cdr1 cdr0 (8-bit) (8-bit) (8-bit) (8-bit) ? 2048 x: the value 0 or 1 corresponding your operation.
48 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa if it needed more higher frequency of pwm, it should be reduced resolution. the bit pol of tm1 decides the polarity of duty cycle. if the duty value is set same to the period value, the pwm output is determined by the bit pol (1: high, 0: low). and if the duty value is set to 00 h , the pwm output is deter- mined by the bit pol (1: low, 0: high). it can be changed duty value when the pwm output. how- ever the changed duty value is output after the current pe- riod is over. and it can be maintained the duty value at present output when changed only period value shown as figure 12-12. as it were, the absolute duty time is not changed in varying frequency. but the changed period val- ue must greater than the duty value. note: if changing the timer1 to pwm function, it should be stop the timer clock firstly, and then set period and duty register value. if user writes register values while timer is in opera- tion, these register could be set with certain values. ex) ldm tm1,#00h ldm t1ppr,#00h ldm t1pdr,#00h ldm pwm0hr,#00h ldm rbfunc,#0001_1100b ldm tm1,#1010_1011b figure 12-10 pwm mode resolution frequency t1ck[1:0] = 00(125ns) t1ck[1:0] = 01(250ns) t1ck[1:0] = 10(1us) 10-bit 7.8khz 3.9khz 0.98khz 9-bit 15.6khz 7.8khz 1.95khz 8-bit 31.2khz 15.6khz 3.90khz 7-bit 62.5khz 31.2khz 7.81khz table 12-2 pwm frequency vs. resolution at 8mhz ? 1 ? 2 ? 8 pwm0hr address : d5h reset value : ----0000 - - - - pwm0hr3 pwm0hr2 pwm0hr1 pwm0hr0 ---- xxxx mux 1 t1cn t1ck[1:0] t1 (8-bit) t1st 0 : stop 1 : clear and start clear comparator comparator t1pdr(8-bit) pwm0hr[1:0] t1ppr(8-bit) pwm0hr[3:2] t1pdr(8-bit) sq r pol pwm0o rb4/ pwm0 t0 clock source f xin tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st x010 xxxx [rbfunc.4] period high duty high slave master bit manipulation not available x: the value 0 or 1 corresponding your operation.
hms87c130xa/120xa/110xa apr. 2001 ver1.0 49 figure 12-11 example of pwm at 8mhz figure 12-12 example of changing the period in absolute duty cycle (@8mhz) f xin t1 pwm ~ ~ ~ ~ ~ ~ 01 02 03 04 05 7f 80 81 3ff 02 03 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ pol=1 pwm pol=0 duty cycle [80h x 125ns = 16us] period cycle [3ffh x 125ns = 127.875us, 7.8khz] pwm0hr = 0ch t1ppr = ffh t1pdr = 80h t1ck[1:0] = 00 (f xin ) pwm0hr3 pwm0hr2 pwm0hr1 pwm0hr0 t1ppr (8-bit) t1pdr (8-bit) period duty 11 ffh 00 80h 00 01 00 source t1 pwm pol=1 duty cycle period cycle [0eh x 1us = 14us, 71khz] pwm0hr = 00h t1ppr = 0eh t1pdr = 05h t1ck[1:0] = 10 (1us) 01 02 03 04 05 06 08 09 0b 0c 0d 0e 01 02 03 04 05 06 07 08 09 0a 01 02 03 04 07 0a 05 [05h x 1us = 5us] duty cycle [05h x 1us = 5us] period cycle [0ah x 1us = 10us, 100khz] duty cycle [05h x 1us = 5us] write t1ppr to 0ah period changed clock
50 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 13. buzzer output function the buzzer driver consists of 6-bit binary counter, the buzzer register bur and the clock selector. it generates square-wave which is very wide range frequency (480 hz~250 khz at f xin = 4 mhz) by user programmable counter. pin rb1 is assigned for output port of buzzer driver by set- ting the bit buzo of rbfunc to 1. the 6-bit buzzer counter is cleared and start the counting by writing signal to the register bur. it is increased from 00h until it matches 6-bit register bur. also, it is cleared by counter overflow and count up to out- put the square wave pulse of duty 50%. the bit 0 to 5 of bur determines output frequency for buzzer driving. frequency calculation is following as shown below. the bits buck1, buck0 of bur selects the source clock from prescaler output. figure 13-1 buzzer driver f buz hz () oscillator frequency 2 prescaler ratio bur 1 + () ------------------------------------------------------------------------------ = bur address : deh reset value : 11111111 buck1 buck0 bur5 bur4 bur3 bur2 bur1 bur0 ? 64 ? 16 ? 32 f xin mux counter (6-bit) bur (6-bit) f/f comparator buck[1:0] rb1/buz pin ? 8 input clock selection 00 : f xin ? 8 01 : f xin ? 16 10 : f xin ? 32 11 : f xin ? 64 buzzer period data buzo [rbfunc.1] bit manipulation not available
hms87c130xa/120xa/110xa apr. 2001 ver1.0 51 14. analog to digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a corresponding 8-bit digital value. the a/d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which gen- erates the result via successive approximation. the analog reference voltage is selected to v dd or av ref by setting of the bit avrefs in rbfunc register. if ex- ternal analog reference av ref is selected, the bit ansel0 should not be set to 1, because this pin is used to an an- alog reference of a/d converter. the a/d module has two registers which are the control register adcm and a/d result register adcr. the adcm register, shown in figure 14-2, controls the opera- tion of the a/d converter module. the port pins can be configure as analog inputs or digital i/o. to use analog inputs, each port is assigned analog input port by setting the bit ansel[7:0] in rafunc register. and selected the corresponding channel to be converted by setting ads[2:0]. the processing of conversion is start when the start bit adst is set to 1. after one cycle, it is cleared by hard- ware. the register adcr contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adcr, the a/d conversion status bit adsf is set to 1, and the a/d interrupt flag adif is set. the block diagram of the a/d module is shown in figure 14-1. the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conver- sion is in process. the conversion time takes maximum 10 us (at f xin =8 mhz). figure 14-1 a/d converter block diagram rb0/an0/av ref ansel0 (rafunc.0) ra1/an1 ansel1 ra2/an2 ansel2 ra3/an3 ansel3 ra4/an4 ansel4 ra5/an5 ansel5 ra6/an6 ansel6 ra7/an7 ansel7 000 001 010 011 100 101 110 111 v dd pin 1 0 avrefs (rbfunc.0) aden s/h successive approximation circuit adif resistor ladder circuit ads[2:0] adcr(8-bit) sample & hold a/d interrupt address : ebh reset value : undefined a/d result register
52 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa figure 14-2 a/d converter registers figure 14-3 a/d converter operation flow a/d converter cautions (1) input range of an0 to an7 the input voltage of an0 to an7 should be within the specification range. in particular, if a voltage above v dd (or av ref ) or below v ss is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. the conversion values of the other channels may also be affected. (2) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins av ref (or v dd ) and an0 to an7. since the effect increases in proportion to the output impedance of the an- alog input source, it is recommended that a capacitor be con- nected externally as shown in figure 14-4 in order to reduce noise. figure 14-4 analog input pin connecting capacitor adcm address : eah reset value : --000001 - - aden ads2 ads1 ads0 adst adsf reserved analog channel select a/d status bit 0 : a/d conversion is in process 1 : a/d conversion is completed a/d start bit 1 : a/d conversion is started after 1 cycle, cleared to 0 0 : bit force to zero 000 : channel 0 (rb0/an0) 001 : channel 1 (ra1/an1) 010 : channel 2 (ra2/an2) 011 : channel 3 (ra3/an3) 100 : channel 4 (ra4/an4) 101 : channel 5 (ra5/an5) 110 : channel 6 (ra6/an6) 111 : channel 7 (ra7/an7) a/d enable bit 1 : a/d conversion is enable 0 : a/d converter module shut off and consumes no operation current a/d control register adcr address : ebh reset value : undefined adcr7 adcr6 adcr5 adcr4 adcr3 adcr2 adcr1 adcr0 a/d result data register enable a/d converter a/d start (adst = 1) nop adsf = 1 a/d input channel select analog reference select read adcr yes no an0~an7 100~1000pf analog input
hms87c130xa/120xa/110xa apr. 2001 ver1.0 53 (3) pins an0/rb0 and an1/ra1 to an7/ra7 the analog input pins an0 to an7 also function as input/ output port (port ra and rb0) pins. when a/d conver- sion is performed with any of pins an0 to an7 selected, be sure not to execute a port input instruction while con- version is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (4) av ref pin input impedance a series resistor string of approximately 10k w is connected be- tween the av ref pin and the v ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the av ref pin and the v ss pin, and there will be a large reference voltage error.
54 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 15. interrupts the hms87c1x0xa interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flags of irqh, irql, interrupt edge selection register (ieds), priority circuit and master enable flag(i flag of psw). the configuration of interrupt circuit is shown in figure 15-1and interrupt priority is shown in table 15-1. the external interrupts int0 and int1 can each be transi- tion-activated (1-to-0, 0-to-1 and both transition). the flags that actually generate these interrupts are bit int0if and int1if in register irqh. when an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. the timer 0 and timer 1 interrupts are generated by t0if and t1if, which are set by a match in their respective tim- er/counter register. the ad converter interrupt is generat- ed by adif which is set by finishing the analog to digital conversion. the watch dog timer interrupt is generated by wdtif which set by a match in watch dog timer register (when the bit wdton is set to 0). the basic interval timer interrupt is generated by bitif which is set by a overflowing of the basic interval timer register(bitr). figure 15-1 block diagram of interrupt function bit bitif wdtif wdt a/d converter timer 1 timer 0 external int. 1 external int. 0 ienh interrupt enable interrupt enable irqh irql interrupt vector address generator internal bus line register (lower byte) internal bus line register (higher byte) release stop to cpu interrupt master enable flag i flag ienl priority control i-flag is in psw, it is cleared by di, set by ei instruction.when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by reti instruction, i-flag is set to 1 by hardware. int0if int1if t0if t1if adif 7 6 5 4 7 6 5 ieds
hms87c130xa/120xa/110xa apr. 2001 ver1.0 55 the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw), the interrupt enable register (ienh, ienl) and the interrupt request flags (in irqh, irql) except power-on reset and software brk interrupt. interrupt enable registers are shown in figure 15-2. these registers are composed of interrupt enable flags of each in- terrupt source, these flags determines whether an interrupt will be accepted or not. when enable flag is 0, a corre- sponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which disables all interrupts at once. figure 15-2 interrupt enable registers and interrupt request registers when an interrupt is occurred, the i-flag is cleared and dis- able any further interrupt, the return address and psw are pushed into the stack and the pc is vectored to. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. the interrupt request flag bit(s) must be cleared by soft- ware before re-enabling interrupts to avoid recursive inter- rupts. the interrupt request flags are able to be read and written. reset/interrupt symbol priority vector addr. hardware reset external interrupt 0 external interrupt 1 timer 0 timer 1 a/d converter watch dog timer basic interval timer reset int0 int1 timer 0 timer 1 a/d c wdt bit - 1 2 3 4 5 6 7 fffe h fffa h fff8 h fff6 h fff4 h ffea h ffe8 h ffe6 h table 15-1 interrupt priority ienh address : e2h reset value : 0000---- int0e int1e t0e t1e - - - - interrupt enable register high ienl address : e3h reset value : 000----- ade wdte bite - - - - - interrupt enable register low irqh address : e4h reset value : 0000---- int0if int1if t0if t1if - - - - interrupt request register high irql address : e5h reset value : 000----- adif wdtif bitif - - - - - interrupt request register low 0 : disable 1 : enable enables or disables the interrupt individually if flag is cleared, the interrupt is disabled. 0 : not occurred 1 : interrupt request is occurred shows the interrupt occurrence
56 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 15.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an in- struction. interrupt acceptance sequence requires 8 f osc (2 m s at f xin =4mhz) after the completion of the current in- struction execution. the interrupt service task is terminat- ed upon execution of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to 0 to temporarily disable the acceptance of any follow- ing maskable interrupts. when a non-maskable inter- rupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. figure 15-3 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to 1 even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i-flag should be set to 1 by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are se- lectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these registers are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. basic interval timer 012 h 0f3 h 0ffe6 h 0ffe7 h 0e h 2f h 0f312 h 0f313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address
hms87c130xa/120xa/110xa apr. 2001 ver1.0 57 the following method is used to save/restore the general- purpose registers. example: register save using push and pop instructions general purpose register save/restore using push and pop instructions; brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b-flag of psw is set to distin- guish brk from tcall 0. each processing step is determined by b-flag as shown in figure 15-4. figure 15-4 execution of brk/tcall0 multi interrupt if two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. if requests of the interrupt are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. however, multiple processing through software for special features is possible. generally when an interrupt is accept- ed, the i-flag is cleared to disable any further interrupt. but as user sets i-flag in interrupt routine, some further inter- rupt can be serviced even if certain interrupt is in progress. figure 15-5 execution of multi interrupt example: even though timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#80h ; enable int0 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#0f0h ; enable all interrupts ldm ienl,#0e0h pop y pop x pop a reti intxx: push a push x push y ;save acc. ;save x reg. ;save y reg. interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1 enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable ei in the timer1 routine.
58 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 15.2 external interrupt the external interrupt on int0 and int1 pins are edge triggered depending on the edge selection register ieds (address 0e6 h ) as shown in figure 15-6. the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. figure 15-6 external interrupt block diagram example: to use as an int0 and int1 : : ; **** set port as an input port rb2 ldm rbio,#1111_1011b ; ; **** set port as an interrupt port ldm rbfunc,#04h ; ; **** set falling-edge detection ldm ieds,#0000_0001b : response time the int0 and int1 edge are latched into int0if and int1if at every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a re- quest is active and conditions are right for it to be acknowl- edged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. the div itself takes twelve cycles. thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. figure 15-7 shows interrupt response timings. figure 15-7 interrupt response timing diagram int0if int0 pin int0 interrupt int1if int1 pin int1 interrupt ieds [0e6 h ] edge selection int0 edge select ext. interrupt edge selection ieds address : 0e6 h reset value : ----0000 00 : int. disable wwwwww 01 : falling 10 : rising 11 : both int1 edge select 00 : int. disable 01 : falling 10 : rising 11 : both register ww interrupt goes active interrupt latched interrupt processing interrupt routine 8 f osc max. 12 f osc
hms87c130xa/120xa/110xa apr. 2001 ver1.0 59 16. watchdog timer the purpose of the watchdog timer is to detect the mal- function (runaway) of program due to external noise or other causes and return the operation to the normal condi- tion. the watchdog timer has two types of clock source. the first type is an on-chip rc oscillator which does not require any external components. this rc oscillator is sep- arate from the external oscillator of the xin pin. but the in- ternal rc oscillated clock source should be activated by execution of stop instruction. it means that the watchdog timer can not run even if the clock on the xin pin of the device has been stopped, for example, by entering the stop mode. the other type is a prescaled system clock. the watchdog timer consists of 7-bit binary counter and the watchdog timer data register. the source clock of wdt is overflow of basic interval timer. when the value of 7-bit binary counter is equal to the lower 7 bits of wdtr, the interrupt request flag is generated. this can be used as wdt interrupt or cpu reset signal in accordance with the bit wdton . note: because the watchdog timer counter is enabled af- ter clearing basic interval timer and setting the watchdog timer register, maximum error of timer is depend on prescaler ratio of basic interval timer. the 7-bit binary counter is cleared by setting wdtcl(bit7 of wdtr) and the wdtcl is cleared automatically after 1 machine cycle. the rc oscillated watchdog timer is activated by setting the bit rcwdt of ckctlr and executing the stop in- struction as shown below. the rc oscillation period is variable according to the tem- perature, v dd and process variations from part to part (ap- proximately, 120~180us at 5v). the following equation shows the rc oscillated watchdog timer time-out. t rcwdt =clk rc 2 8 [ wdtr.6~0]+(clk rc 2 8 )/2 where, clk rc = 120~180us in addition, this watchdog timer can be used as a simple 7- bit timer by interrupt wdtif. the interval of watchdog timer interrupt is decided by basic interval timer. interval equation is as below. t wdt = [wdtr.6~0] interval of bit figure 16-1 block diagram of watchdog timer : ldm ckctlr,#3fh ; enable the rc-osc wdt ldm wdtr,#0ffh ; set the wdt period stop ; enter the stop mode nop nop ; rc-osc wdt running : ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 0 1 mux 8 3 f xin bitr (8-bit) bts[2:0] internal rc osc basic interval timer interrupt btcl clear watchdog timer bitif 7-bit counter wdtr (8-bit) ofd wdtcl wdton interrupt request cpu reset 1 0 clock control register ckctlr address : ech reset value : -0010111 - wakeup rcwdt wdton btcl bts2 bts1 bts0 - 0x1 xxxx watchdog timer register wdtr address : edh reset value : 01111111 wdtcl 7-bit watchdog counter register overflow detection bit manipulation not available bit manipulation not available stop wakeup rcwdt
60 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 17. power saving mode for applications where power consumption is a critical factor, device provides three kinds of power saving func- tions, stop mode, wake-up timer mode and internal rc- oscillated watchdog timer mode. the power saving function is activated by execution of stop instruction after setting the corresponding bit (wakeup, rcwdt) of ckctlr. table 17-1 shows the status of each power saving mode note: before executing stop instruction, clear all in- terrupt request flag. because if the interrupt re- quest flag is set before stop instruction, the mcu runs as if it doesnt perform stop instruction, even though the stop instruction is completed. so insert two lines to clear all interrupt request flags (irqh, irql) before stop instruction as shown each ex- ample. 17.1 stop mode in the stop mode, the on-chip oscillator is stopped. with the clock frozen, all functions are stopped, but the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port di- rection registers. oscillator stops and the systems internal operations are all held up. ? the states of the ram, registers, and latches valid immediately before the system is put in the stop state are all held. ? the program counter stop the address of the instruction to be executed after the instruction stop which starts the stop operating mode. the stop mode is activated by execution of stop in- struction after setting the bit wakeup and rcwdt of ckctlr to 00. (this register should be written by byte operation. if this register is set by bit manipu- lation instruction, for example set1 or clr1 instruc- tion, it may be undesired operation) in the stop mode of operation, v dd can be reduced to min- imize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level, before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. note: after stop instruction, at least two or more nop instruction should be written ex) ldm ckctlr ,#0 00 0_1110b ldm irqh ,#0 ldm irql ,#0 stop nop nop in the stop operation, the dissipation of the power asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current peripheral stop wake-up timer internal rc-wdt ram retain retain retain control registers retain retain retain i/o ports retain retain retain cpu stop stop stop timer0 stop operation stop oscillation stop oscillation stop prescaler stop ? 2048 only stop internal rc oscillator stop stop oscillation entering condition ckctlr[6,5] 00 1x 01 power saving release source reset, int0, int1 reset, int0, int1, timer0 reset, int0, int1, rc-wdt table 17-1 power saving mode
hms87c130xa/120xa/110xa apr. 2001 ver1.0 61 flows when the input level is stable at the power voltage level (v dd /v ss ), however, when the input level gets high- er than the power voltage level (by approximately 0.3 to 0.5v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. release the stop mode the exit from stop mode is hardware reset or external in- terrupt. reset re-defines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their val- ues. after releasing stop mode, instruction execution is divid- ed into two ways by i-flag(bit2 of psw). if i-flag = 1, the normal interrupt response takes place. if i- flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vec- tor to interrupt service routine. (refer to figure 17-1) when exit from stop mode by external interrupt, enough oscillation stabilization time is required to normal opera- tion. figure 17-2 shows the timing diagram. when release the stop mode, the basic interval timer is activated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant prescaler di- vide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from stop mode is shown in figure 17-3. minimizing current consumption in stop mode the stop mode is designed to reduce power consumption. to minimize the current consumption during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. weak pull-ups on port pins should be turned off, if possible. all inputs should be either as v ss or at v dd (or as close to rail as possible). an intermediate voltage on an input pin causes the input buffer to draw a significant amount of current. figure 17-1 stop releasing flow by interrupts figure 17-2 timing of stop mode release by external interrupt iexx =0 =1 stop instruction stop mode interrupt request stop mode release i-flag =1 interrupt service routine next instruction =0 master interrupt enable bit psw[2] corresponding interrupt enable bit (ienh, ienl) ~ ~ stop mode normal operation oscillator (x in pin) ~ ~ ~ ~ n+1 n n+2 00 01 fe ff 00 01 n-1 n-2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clear basic interval timer stop instruction execution normal operation stabilization time t st > 20ms internal clock external interrupt bit counter ~ ~
62 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa figure 17-3 timing of stop mode release by reset 17.2 wake-up timer mode in the wake-up timer mode, the on-chip oscillator is not stopped. except the prescaler (only 2048 divided ratio) and timer0, all functions are stopped, but the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction registers. the wake-up timer mode is activated by execution of stop instruction after setting the bit wakeup of ckctlr to 1. (this register should be written by byte operation. if this register is set by bit manipulation instruction, for example set1 or clr1 instruction, it may be undesired operation) note: after stop instruction, at least two or more nop in- struction should be written ex) ldm tdr0,#0ffh ldm tm0,#0001_1011b ldm ckctlr,#0100_1110b ldm irqh,#0 ldm irql,#0 stop nop nop in addition, the clock source of timer0 should be select- ed to 2048 divided ratio. otherwise, the wake-up func- tion can not work. and the timer0 can be operated as 16-bit timer with timer1 (refer to timer function). the period of wake-up function is varied by setting the tim- er data register 0, tdr0. release the wake-up timer mode the exit from wake-up timer mode is hardware reset, timer0 overflow or external interrupt. reset re-defines all the control registers but does not change the on-chip ram. external interrupts and timer0 overflow allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i- flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vec- tor to interrupt service routine (refer to figure 17-1). when exit from wake-up timer mode by external inter- rupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. because this mode do not stop the on-chip oscillator shown as figure 17-4. figure 17-4 wake-up timer mode releasing by external interrupt or timer0 interrupt ~ ~ stop mode oscillator (x in pin) ~ ~ ~ ~ ~ ~ stop instruction execution stabilization time t st = 64ms @4mhz internal clock internal ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ reset reset time can not be controlled by software wake-up timer mode oscillator (x in pin) ~ ~ stop instruction normal operation normal operation cpu clock request interrupt ~ ~ ~ ~ execution do not need stabilization time (stop the cpu clock) ~ ~
hms87c130xa/120xa/110xa apr. 2001 ver1.0 63 17.3 internal rc-oscillated watchdog timer mode in the internal rc-oscillated watchdog timer mode, the on-chip oscillator is stopped. but internal rc oscillation circuit is oscillated in this mode. the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction regis- ters. the internal rc-oscillated watchdog timer mode is activated by execution of stop instruction after set- ting the bit wakeup and rcwdt of ckctlr to 01. (this register should be written by byte opera- tion. if this register is set by bit manipulation instruc- tion, for example set1 or clr1 instruction, it may be undesired operation) note: after stop instruction, at least two or more nop in- struction should be written ex) ldm wdtr,#1111_1111b ldm ckctlr,#0010_1110b ldm irqh,#0 ldm irql,#0 stop nop nop release the internal rc-oscillated watchdog timer mode the exit from internal rc-oscillated watchdog timer mode is hardware reset or external interrupt. reset re-de- fines all the control registers but does not change the on- chip ram. external interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. in this case, if the bit wdton of ckctlr is set to 0 and the bit wdte of ienh is set to 1, the device will exe- cute the watchdog timer interrupt service routine.(figure 17-5) however, if the bit wdton of ckctlr is set to 1, the device will generate the internal reset signal and execute the reset processing. (figure 17-6) if i-flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vector to interrupt service routine (refer to figure 17-1). when exit from internal rc-oscillated watchdog timer mode by external interrupt, the oscillation stabilization time is required for normal operation. figure 17-5 shows the timing diagram. when release the internal rc-oscil- lated watchdog timer mode, the basic interval timer is ac- tivated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant pres- caler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from internal rc-oscillated watchdog tim- er mode is shown in figure 17-6. figure 17-5 internal rcwdt mode releasing by external interrupt or wdt interrupt ~ ~ rcwdt mode normal operation oscillator (x in pin) ~ ~ ~ ~ n+1 n n+2 00 01 fe ff 00 00 n-1 n-2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clear basic interval timer stop instruction execution normal operation stabilization time t st > 20ms internal clock external interrupt bit counter ~ ~ internal rc clock (or wdt interrupt)
64 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa figure 17-6 internal rcwdt mode releasing by reset 17.4 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. note: in the stop operation, the power dissipation asso- ciated with the oscillator and the internal hardware is lowered; however, the power dissipation associat- ed with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level becomes higher than the power voltage level (by approximately 0.3v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. it should be set properly that current flow through port doesn't exist. first conseider the setting to input mode. be sure that there is no current flow after considering its relationship with external circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesnt flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if uncertain voltage level (not v ss or v dd ) is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. setting to high or low is decided considering its relationship with external circuit. for example, if there is external pull-up re- sistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low. ~ ~ oscillator (x in pin) ~ ~ ~ ~ ~ ~ ~ ~ internal clock internal rc clock ~ ~ stop instruction execution stabilization time t st = 64ms @4mhz internal ~ ~ ~ ~ ~ ~ reset by wdt reset reset rcwdt mode time can not be controlled by software
hms87c130xa/120xa/110xa apr. 2001 ver1.0 65 figure 17-7 application example of unused input port figure 17-8 application example of unused output port input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configure as an input, input level should be closed to 0v or 5v to avoid power consumption. output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port.
66 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 18. reset the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, while the oscillator running. after reset, 64ms (at 4 mhz) add with 7 oscillator periods are required to start execution as shown in figure 18-1. internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before reading or testing it. initial state of each register is shown as table 8-1. figure 18-1 timing diagram after reset ? power-on reset (por) the hms87c130xa incorporates on-chip power-on re- set (por) circuitry which provides an internal chip reset for most power-up situations. to use this feature, the user merely ties the reset pin to v dd and setting the poren bit of config register ( refer to figure 20-1). a power-on reset pulse is generated on-chip when v dd rise is detected approximately 1v. to take an advantage of the power-on reset, just tie the reset pin directly ( or through the resistor ) to v dd . figure 18-2 time-out sequence on power-up (reset tied to v dd ): fast v dd rise time a power-up example where reset is not tied to v dd is shown in figure 18-2. v dd is allowed to rise and stabilize before bringing reset high. the chip will actually come out of reset and start the basic interval timer after reset goes high. in figure 18-3, the on-chip power-on reset feature is be- ing used (reset and v dd are tied together). the v dd is stable before the basic interval timer times out and there is no problem in getting a proper reset. however, figure 18- 4 depicts a problem situation where v dd rises too slowly. main program oscillator (x in pin) ? ? fffe ffff stabilizing time t st = 64ms at 4mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ v dd reset internal reset basic interval timer start
hms87c130xa/120xa/110xa apr. 2001 ver1.0 67 the time between when the basic interval timer senses a high on the reset pin, and when the reset pin (and v dd ) actually reach their full value, is too long. in this sit- uation, when the basic interval timer times out, v dd has not reached the v dd (min) value and the chip is, therefore, not guaranteed to function correctly. for such situations, we recommend that external r circuits be used to achieve longer por delay times ( figure 18-5). the por circuit does not produce an internal reset when v dd declines note: when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be meet to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met.. figure 18-3 time-out sequence on power-up (reset tied to v dd ): fast v dd rise time figure 18-4 time-out sequence on power-up (reset tied to v dd ): slow v dd rise time figure 18-5 external poweron reset circuit (for slow v dd power-up) v dd reset internal por internal reset basic interval timer start v dd reset internal por internal reset basic interval timer start reset - external power-on reset circuit is required only if vdd power-up is too slow. the diode d helps discharge the capacitor quickly when vdd powers down. - r < 40 k w is recommended to make sure that voltage drop across r does not violate the device electrical specifi- cation . - r1 = 100 w to 1k w will limit any current flowing into reset from external capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or electrical overstress (eos). r r1 d c v dd v dd
68 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 19. power fail processor the hms87c1x0xa has an on-chip power fail detection circuitry to immunize against power noise. a power fail detector register, pfdr can enable (if clear/pro- grammed) or disable (if set) the power fail detect circuitry. if v dd falls below 2.4~2.6v(or 1.6~1.8v) range for longer than 50 ns, the power fail situation may reset mcu or halt the system clock according to pfs bit of pfdr. and pow- er fail detect level is selectable by programming the bit pfdlevel of config register when program the otp. as below pfdr register is not implemented on the in-cir- cuit emulator, user can not experiment with it. therefore, after final development of user program, this function may be experimented. note: power fail detect level is decided by setting the bit pfdlevel of config register (refer to figure 20- 1. figure 19-1 power fail detector pfdr address : efh reset value : ----0100 - - - - pfdopr pfdis pfdm pfs reserved power fail status 0 : normal operate 1 : this bit force to 1 when operation mode 0 : system clock freeze during power fail 1 : mcu will be reset during power fail disable flag 0 : power fail detection enable 1 : power fail detection disable power fail detector register power fail was detected pfd operation disable flag 0 : power fail detection enable 1 : power fail detection disable power fail detection circuit power noise pfdis pfdopr pfdm to reset circuit system clock freeze pfs but can read pfs
hms87c130xa/120xa/110xa apr. 2001 ver1.0 69 figure 19-2 example s/w of reset by power fail figure 19-3 power fail processor situations funtion execution initialize ram data pfs =1 no reset vector initialize all ports initialize registers ram clear yes skip the initial routine internal reset internal reset internal reset v dd v dd v dd pfv dd max pfv dd min pfv dd max pfv dd min pfv dd max pfv dd min 64ms 64ms t < 64ms 64ms when pfdm = 1 v dd v dd pfv dd max pfv dd min pfv dd max pfv dd min when pfdm = 0 system clock system clock
70 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa 20. otp programming the hms87c130xa is one-time prom(otp) microcon- troller with 4k/2k bytes electrically programmable read only memory. to programming the otp device, user must use the uni- versal programmer which is support hynix microcontrol- lers. 20.1 device configuration area the device configuration area can be programmed or left unprogrammed to select device configuration such as secu- rity bit, power on reset, rc-oscillation, pfd level select and open drain port selection . this area is not accessible during normal execution but is readable and writable during program / verify. figure 20-1 device configuration area 0 : allow code read out 1 : prohibit code read out security bit 0 : pfd level high (2.4~2.6v) 1 : pfd level low (1.6~1.8v) pfd level select config address : 707fh - - poren opdr1 opdr0 lock pfd rc_opt configuration register level 0 : normal oscillator 1 : external rc oscillator rc otion 00 : normal port 01 : open drain ra0 open drain port selection 10 : open drain ra0/rb2 11 : open drain ra0/rb2/rb3/rc0 0 : power on reset disable 1 : power on reset enable power on reset
hms87c130xa/120xa/110xa apr. 2001 ver1.0 71 figure 20-2 pin assignment ( hms1304/2a ) v dd 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 11 12 14 13 v pp a_d0 a_d1 a_d2 a_d3 eprom enable a_d7 a_d6 a_d5 a_d4 ctl2 ctl1 ctl0 v ss nc pin no. user mode eprom mode pin name pin name description 1 ra4 (an4) a_d4 address input data input/output a12 a4 d4 2 ra5 (an5) a_d5 a13 a5 d5 3 ra6 (an6) a_d6 a14 a6 d6 4 ra7 (an7) a_d7 a15 a7 d7 5 v dd v dd connect to v dd (6.0v) 6 rd0 ctl0 read/write control address/data control 7 rd1 ctl1 8 rbb0/an0/avref ctl2 9~14 rb1~4, rd2~3 v dd connect to v dd (6.0v) 15 x in eprom enable high active, latch address in falling edge 16 x out nc no connection 17 reset v pp programming power (0v, 12.75v) 18 v ss v ss connect to v ss (0v) 19,20 rc0, 1 v dd connect to v dd (6.0v) 21 ra0 (ec0) a_d0 address input data input/output a8 a0 d0 22 ra1 (an1) a_d1 a9 a1 d1 23 ra2 (an2) a_d2 a10 a2 d2 24 ra3 (an3) a_d3 a11 a3 d3 table 20-1 pin description in eprom mode ( hms1304/2a )
72 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa figure 20-3 pin assignment ( hms1204/2a ) pin no. user mode eprom mode pin name pin name description 1 ra4 (an4) a_d4 address input data input/output a12 a4 d4 2 ra5 (an5) a_d5 a13 a5 d5 3 ra6 (an6) a_d6 a14 a6 d6 4 ra7 (an7) a_d7 a15 a7 d7 5 v dd v dd connect to v dd (6.0v) 6 rb0/an0/avref ctl0 read/write control address/data control 7 rb1/buz ctl1 8 rb2/int0 ctl2 9,10 rb3~4 v dd connect to v dd (6.0v) 11 x in eprom enable high active, latch address in falling edge 12 x out nc no connection 13 reset v pp programming power (0v, 12.75v) 14 v ss v ss connect to v ss (0v) 15,16 rc0, 1 v dd connect to v dd (6.0v) 17 ra0 (ec0) a_d0 address input data input/output a8 a0 d0 18 ra1 (an1) a_d1 a9 a1 d1 19 ra2 (an2) a_d2 a10 a2 d2 20 ra3 (an3) a_d3 a11 a3 d3 table 20-2 pin description in eprom mode ( hms1204/2a ) v dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v pp a_d0 a_d1 a_d2 a_d3 eprom enable a_d7 a_d6 a_d5 a_d4 ctl2 ctl1 ctl0 v ss nc
hms87c130xa/120xa/110xa apr. 2001 ver1.0 73 figure 20-4 pin assignment ( hms1104/2a ) pin no. user mode eprom mode pin name pin name description 1 ra4 (an4) a_d4 address input data input/output a12 a4 d4 2 ra5 (an5) a_d5 a13 a5 d5 3 ra6 (an6) a_d6 a14 a6 d6 4 ra7 (an7) a_d7 a15 a7 d7 5 v dd v dd connect to v dd (6.0v) 6 rb0/an0/avref ctl0 read/write control address/data control 7 rb2/int0 ctl1 8 rb4/pwm/comp ctl2 9 x in eprom enable high active, latch address in falling edge 10 x out nc no connection 11 reset v pp programming power (0v, 12.75v) 12 v ss v ss connect to v ss (0v) 13 ra0 (ec0) a_d0 address input data input/output a8 a0 d0 14 ra1 (an1) a_d1 a9 a1 d1 15 ra2 (an2) a_d2 a10 a2 d2 16 ra3 (an3) a_d3 a11 a3 d3 table 20-3 pin description in eprom mode ( hms1104/2a ) v dd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v pp a_d0 a_d1 a_d2 a_d3 eprom enable a_d7 a_d6 a_d5 a_d4 ctl2 ctl1 ctl0 v ss nc
74 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa figure 20-5 timing diagram in program (write & verify) mode figure 20-6 timing diagram in read mode v pp ctl0 ~ ~ high 8bit ha la data in data ~ ~ ~ ~ ~ ~ ~ ~ out la data in data out eprom enable ctl1 ctl2 a_d7~ v dd v dd1h 0v 0v 0v address input low 8bit address input write mode verify low 8bit address input write mode verify a_d0 t vdds t vppr t vpps ~ ~ v dd1h v dd1h v ihp ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t hld1 t hld2 t set1 t dly1 t dly2 t cd1 t cd1 t cd1 t cd1 v pp ctl0 high 8bit ha la data la data data eprom enable ctl1 ctl2 a_d7~ v dd v dd2h 0v 0v 0v address input low 8bit address input data a_d0 t vdds t vppr t vpps v dd2h v dd2h v ihp t hld1 t set1 t dly1 t cd1 t cd2 t cd2 t cd1 ha la output low 8bit address input high 8bit address input low 8bit address input data output data output after input a high address, output data following low address input another high address step
hms87c130xa/120xa/110xa apr. 2001 ver1.0 75 parameter symbol min typ max unit programming supply current i vpp --50ma supply current in eprom mode i vddp --20ma v pp level during programming v ihp 12.5 12.75 13 v v dd level in program mode v dd1h 5.566.6v v dd level in read mode v dd2h -2.7-v ctl2~0 high level in eprom mode v ihc 0.8v dd --v ctl2~0 low level in eprom mode v ilc -- 0.2v dd v a_d7~a_d0 high level in eprom mode v ihad 0.9v dd --v a_d7~a_d0 low level in eprom mode v ilad -- 0.1v dd v v dd saturation time t vdds 1- -ms v pp setup time t vppr --1ms v pp saturation time t vpps 1- -ms eprom enable setup time after data input t set1 200 ns eprom enable hold time after t set1 t hld1 500 ns eprom enable delay time after t hld1 t dly1 200 ns eprom enable hold time in write mode t hld2 100 ns eprom enable delay time after t hld2 t dly2 200 ns ctl2,1 setup time after low address input and data input t cd1 100 ns ctl1 setup time before data output in read and verify mode t cd2 100 ns table 20-4 ac/dc requirements for program/read mode
76 apr. 2001 ver 1.0 hms87c130xa/120xa/110xa figure 20-7 programming flow chart start set v dd =v dd1h set v pp =v ihp verify blank first address location eprom write n=1 verify pass last address apply 3n program cycle 100us program time next address location n > 25 report programming failure report programming failure verify for all address verify ok report verify failure report programming ok v dd =v pp =0v end no yes yes yes yes yes no no no no
hms87c130xa/120xa/110xa apr. 2001 ver1.0 77 figure 20-8 reading flow chart start set v dd =v dd2h set v pp =v ihp last address first address location v dd =0v report read ok v pp =0v next address location verify for all address end no yes
appendix
hms871c130xa/120xa/110xa apr. 2001 ver 1.0 i appendix a. instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
hms87c130xa/120xa/110xa ii apr. 2001 ver 1.0 b. instruction set 1. arithmetic/ logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ? ( a ) + ( m ) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ? ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents 22 cmp dp 45 2 3 ( a ) - ( m ) 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : ( dp ) ? ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----z- 39 dec dp a9 2 4 m ? ( m ) - 1 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 42 dec x af 1 2 43 dec y be 1 2 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 0 0 c 7654321
hms871c130xa/120xa/110xa apr. 2001 ver 1.0 iii no. mnemonic op code byte no cycle no operation flag nvgbhizc 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ? ( a ) ? ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----z- 54 inc dp 89 2 4 m ? ( m ) + 1 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 57 inc x 8f 1 2 58 inc y 9e 1 2 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ? ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry 81 sbc dp 25 2 3 a ? ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- 0 0 c 7654321 0 c 7654321 0c 7654321
hms87c130xa/120xa/110xa iv apr. 2001 ver 1.0 2. register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ? ( m ) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8 lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ? ( m ) , x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) ? imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ? ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ? ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) ? a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) ? x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) ? y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a ? x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp ? x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a ? y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y --------
hms871c130xa/120xa/110xa apr. 2001 ver 1.0 v 3. 16-bit operation 4. bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ? ( ya ) + ( dp +1 ) ( dp ) nv--h-zc 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) - (dp+1)(dp) n-----zc 3decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ? ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ? ( dp+1) ( dp ) + 1 n-----z- 5 ldya dp 7d 2 5 load ya ya ? ( dp +1 ) ( dp ) n-----z- 6 stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ? ya -------- 7 subw dp 3d 2 5 16-bits substact without carry ya ? ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ? ( a ) ( m ) , n ? ( m 7 ) , v ? ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ? 0 -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -------- 7 clrc 20 1 2 clear c-flag : c ? 0 -------0 8 clrg 40 1 2 clear g-flag : g ? 0 --0----- 9 clrv 80 1 2 clear v-flag : v ? 0 -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? ( c ) ? ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? ( c ) ? ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ? ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ? ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ? ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? ( c ) ~( m .bit ) -------c 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ? 1 -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ? 1 -------- 19 setc a0 1 2 set c-flag : c ? 1 -------1 20 setg c0 1 2 set g-flag : g ? 1 --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) ? c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ? ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ? ( m ) ( a ) n-----z-
hms87c130xa/120xa/110xa vi apr. 2001 ver 1.0 5. branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ? ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ? ( pc ) + rel 5 bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ? ( pc ) + rel -------- 6 bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ? ( pc ) + rel -------- 7 beq rel f0 2 2/4 branch if equal if ( z ) = 1 , then pc ? ( pc ) + rel -------- 8 bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ? ( pc ) + rel -------- 9 bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ? ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if minus if ( n ) = 0 , then pc ? ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ? ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ? ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ? ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ? ( pc h ), sp ? sp - 1, m(sp) ? (pc l ), sp ? sp - 1, if !abs, pc ? abs ; if [dp], pc l ? ( dp ), pc h ? ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) 1 ( m ) , then pc ? ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 1 0 , then pc ? ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc ? jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ), sp ? sp - 1, pc l ? ( upage ), pc h ? 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ),sp ? sp - 1, pc l ? (table vector l), pc h ? (table vector h) --------
hms871c130xa/120xa/110xa apr. 2001 ver 1.0 vii 6. control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt : b ? 1, m(sp) ? (pc h ), sp ? sp-1, m(s) ? (pc l ), sp ? sp - 1, m(sp) ? (psw), sp ? sp -1, pc l ? ( 0ffde h ) , pc h ? ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable interrupts : i ? 0 -----0-- 3 ei e0 1 3 enable interrupts : i ? 1 -----1-- 4 nop ff 1 2 no operation -------- 5 pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) 6 pop x 2d 1 4 sp ? sp + 1, x ? m( sp ) -------- 7 pop y 4d 1 4 sp ? sp + 1, y ? m( sp ) 8 pop psw 6d 1 4 sp ? sp + 1, psw ? m( sp ) restored 9 push a 0e 1 4 m( sp ) ? a , sp ? sp - 1 10 push x 2e 1 4 m( sp ) ? x , sp ? sp - 1 -------- 11 push y 4e 1 4 m( sp ) ? y , sp ? sp - 1 12 push psw 6e 1 4 m( sp ) ? psw , sp ? sp - 1 13 ret 6f 1 5 return from subroutine sp ? sp +1, pc l ? m( sp ), sp ? sp +1, pc h ? m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp ? sp +1, psw ? m( sp ), sp ? sp + 1, pc l ? m( sp ), sp ? sp + 1, pc h ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------

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